1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a MOS (Metal Oxide Semiconductor) device and a method for operating an array structure comprising the same devices.
2. Description of the Related Art
The prosperous development of communication and network is attributed to the fast advancing IC technology. The advance of IC technology is motivated by the persistent dimensional reduction, which decreases power consumption, increases switching speed, promotes integration density, and upgrades performance (such as the performance of data storage, logic operation, and signal processing). For a logic device, high operation speed relies on a sufficient saturation drain current and a low gate capacitance, and low power consumption relies on a further lower leakage current.
For a MOS (Metal Oxide Semiconductor) device, the size thereof is 3-dimensionally reduced. As shown in FIG. 1, a conventional MOS device comprises a substrate 10 having a source 102, a drain 104 and a channel 101 thereinside, a gate dielectric layer 12 formed over the substrate 10 and a gate layer 14 formed over the gate dielectric layer 12. For a MOS device, all structural factors influence the performance. Therefore, in addition to the length, width and height of the entire structure, the thickness of the gate dielectric layer 12, the junction depths of the source 102 and the drain 104, etc., also influence the performance of the MOS device. Via reducing the length and width of a MOS device, the integration density is promoted. Besides, decreasing the length of the channel 101 can increases the efficiency of driving power because the required driving current is inversely proportional to the length of the channel 101. The bottleneck of the MOS device fabrication process is primarily in photolithography. As the electric characteristics required by the source 102 and the drain 104 is different from that required by the channel 101, the conventional MOS device fabrication process is pretty complicated. The diffusion problem between the channel 101 and the source 102/drain 104 usually degrades the miniaturization capability. Due to the electric characteristics of the channel 101, the source 102 and the drain 104, a conventional MOS device has an inversion layer 141, which is below the gate and implements the reading activities of the device. However, an induced current, which inactivates the electric characteristics of the MOS device, is created when carriers drift across the inversion layer 141. The short-channel effect and the narrow-channel effect on a MOS device also need to be overcome. Modifying the sectional structural factors, such as decreasing the junction depth and the thickness of the gate dielectric layer 12, increasing the concentration of the implanted ions of the substrate 10, etc., is usually used to reduce the influence of the short-channel effect.
In the conventional technology, the abovementioned decreasing the junction depth and increasing the implanted-ion concentration of the substrate are realized via the means of ion implantation. To reach the specified depth, the ions should be accelerated to a sufficient speed. The concentration of the implanted ion can be precisely controlled via process parameters.
In the current MOS devices, different ions with different concentrations are respectively implanted into different regions of the substrate to prevent from the problems caused by the miniaturization of a MOS device. However, device miniaturization also makes the ion-implanted regions and the spacing between the ion-implanted regions become smaller. Thus, the structure of the overall MOS device becomes more complicated, which results in a higher process complexity and a lower device precision.
Refer to FIG. 2. A U.S. Pat. No. 6,704,253 disclosed a memory device, wherein a plurality of layers is formed over the substrate 20. The layers between two conduction layers 21 and 25 form a memory unit, including a semiconductor layer 22, a dielectric storage layer 26, a lightly-doped layer 23 and a heavily-doped layer 24. However, in addition to the complicated multi-layer structure, the layers must be further separately etched to obtain specified patterns. Therefore, the conventional memory device has a very complicated fabrication process and needs higher material and fabrication costs.
Accordingly, the present invention proposes a metal oxide semiconductor device and a method for operating the same to solve the abovementioned problems.